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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Triple Differential 2:1 Multiplexer
The MC10E457/100E457 is a 3-bit differential 2:1 multiplexer. The fully differential data path makes the device ideal for multiplexing low skew clock or other skew sensitive signals. Multiple VBB pins are provided to ease AC coupling input signals. The higher frequency outputs provide the device with a >1.0GHz bandwidth to meet the needs of the most demanding system clock. Both, separate selects and a common select, are provided to make the device well suited for both data path and random logic applications. The differential inputs have internal clamp structures which will force the Q output of a gate in an open input condition to go to a LOW state. Thus, inputs of unused gates can be left open and will not affect the operation of the rest of the device. Note that the input clamp will take affect only if both inputs fall 2.5V below VCC.
MC10E457 MC100E457
TRIPLE DIFFERENTIAL 2:1 MULTIPLEXER
* * * * * *
Differential D and Q; VBB available 700ps Max. Propagation Delay High Frequency Outputs Separate and Common Select Extended 100E VEE Range of -4.2V to -5.46V Internal 75k Input Pulldown Resistors
FN SUFFIX PLASTIC PACKAGE CASE 776-02
Pinout: 28-Lead PLCC (Top View)
SEL2 D2a 24 D2a 23 VBB 22 D2b 21 D2b COMSEL 20 19 18 17 16 15 14 13 12 5 SEL0 6 D0a 7 D0a 8 VBB 9 D0b 10 11 Q2 Q2 VCC Q1 Q1 Q0 Q0
PIN NAMES
Pin Dn[0:2]; Dn[0:2] SEL COMSEL VBB Q[0:2], Q[0:2] Function Differential Data Inputs Individual Select Input Common Select Input VBB Reference Output Differential Data Outputs SEL1 D1a D1a VEE VBB 26 27 28 1 2 3 4
25
FUNCTION TABLE
SEL H L Data a b
D1b D1b
D0b VCCO
* All VCC and VCCO pins are tied together on the die.
12/93
(c) Motorola, Inc. 1996
2-1
REV 2
MC10E457 MC100E457
LOGIC DIAGRAM
D0a D0a D0b D0b SEL0 H 2:1 MUX L
Q0 Q0
D1a D1a D1b D1b SEL1
H 2:1 MUX L Q1 Q1
D2a D2a D2b D2b SEL2
H 2:1 MUX L
Q2 Q2
COMSEL VBB
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
-40C Symbol VBB Characteristic Output Reference Voltage 10E 100E Input HIGH Current Power Supply Current 10E 100E Input Sensitivity Commom Mode Range 50 -1.5 0 92 92 Min -1.43 -1.38 Typ Max -1.30 -1.26 150 Min -1.38 -1.38 0C Typ Max -1.27 -1.26 150 Min -1.35 -1.38 25C Typ Max -1.25 -1.26 150 Min -1.31 -1.38 85C Typ Max -1.19 -1.26 150 A mA 110 110 50 -1.5 0 92 92 110 110 50 -1.5 0 92 92 110 110 50 -1.5 0 92 106 110 127 mV V 1 2 Unit V Cond
IIH IEE
VPP(DC) VCMR
1. Differential input voltage required to obtain a full ECL swing on the outputs. 2. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to VPP(min).
MOTOROLA
2-2
ECLinPS and ECLinPS Lite DL140 -- Rev 4
MC10E457 MC100E457
AC CHARACTERISTICS (VEE = VEE (min) to VEE (max); VCC = VCCO = GND)
0C Symbol tPLH tPHL Characteristic Propagation Delay to Output D (Differential) D (Single-Ended) SEL COMSEL Within-Device Skew Duty Cycle Skew Minimum Input Swing Rise/Fall Time tPLH - tPHL 150 125 275 500 Min 325 275 300 325 Typ 475 475 500 525 40 10 150 150 275 450 Max 700 750 775 800 Min 375 325 350 375 0C to 85C Typ 475 475 500 525 40 10 Max 650 700 725 750 ps ps mV ps 1 2 3 20-80% Unit ps Condition
tskew tskew VPP(AC) tr/tf
1. Within-device skew is defined as identical transitions on similar paths through a device. 2. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point of the outputs. 3. Minimum input swing for which AC parameters are guaranteed.
ECLinPS and ECLinPS Lite DL140 -- Rev 4
2-3
MOTOROLA
MC10E457 MC100E457
OUTLINE DIMENSIONS
FN SUFFIX PLASTIC PLCC PACKAGE CASE 776-02 ISSUE D
0.007 (0.180) U T L -M
M
B -NY BRK
M
S
N
S S
0.007 (0.180)
T L -M
N
S
D Z -L-M-
W
28 1
D X VIEW D-D G1 0.010 (0.250)
S
V
T L -M
S
N
S
A Z R
0.007 (0.180) 0.007 (0.180)
M
T L -M T L -M
S
N N
S
H
S
0.007 (0.180)
M
T L -M
S
N
S
M
S
C
E G G1 0.010 (0.250)
S
K1 0.004 (0.100) J -TSEATING PLANE
K F VIEW S 0.007 (0.180)
M
VIEW S T L -M
S
T L -M
S
N
S
N
S
NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIM R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 -- 0.025 -- 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 -- 0.020 2 10 0.410 0.430 0.040 --
MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 -- 0.64 -- 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 -- 0.50 2 10 10.42 10.92 1.02 --
MOTOROLA
2-4
ECLinPS and ECLinPS Lite DL140 -- Rev 4
MC10E457 MC100E457
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JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
ECLinPS and ECLinPS Lite DL140 -- Rev 4 2-5
*MC10E457/D*
MC10E457/D MOTOROLA

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